JEDEC JESD47L（中英文对照版）.pdf

JEDEC

STANDARD

电子工程设

计发展联合

协会（现为

固态技术协

会）标准

Stress-Test-DrivenQualificationof

IntegratedCircuits

集成电路基于压力测试的考核

JESD47L

(RevisionofJESD47KdatedAugust2018)

DECEMBER2022

JEDECSOLIDSTATETECHNOLOGYASSOCIATION

JEDEC固态技术协会

JEDECStandardNo.47L

STRESS-TEST-DRIVENQUALIFICATIONOFINTEGRATED

CIRCUITS

Contents

Page

1Scope1

2NormativeReferences2

2.1Military2

2.2Industrial2

3GeneralRequirements3

3.1Objective3

3.2QualificationFamily3

3.3LotRequirements3

3.4ProductionRequirements3

3.5ReusabilityofTestSamples3

3.6DefinitionofElectricalTestFailureAfterStressing4

3.7RequiredStressTestsforQualification4

3.8Pass/FailCriteria4

4QualificationandRequalifications5

4.1QualificationofaNewDevice5

4.2RequalificationofaChangedDevice5

4.2.1ProcessChangeNotification5

4.2.2ChangesRequiringRequalification6

4.2.3CriteriaforPassingRequalification6

5QualificationTests6

5.1GeneralTests6

5.2DeviceSpecificTests6

5.3WearoutReliabilityTests6

5.4Flammability/OxygenIndex7

5.5DeviceQualificationRequirements7

5.6Non-hermeticPackageQualificationTestRequirements13

5.7HermeticPackageQualificationTests16

5.8