EDA技术与应用课后习题答案（2）.docx

EDA技术与应用课后习题答案（2）

EDA技术与应用课后习题答案大全

ENDIF;

ENDPROCESS;

PR02:PROCESS(s1)

BEGIN

IFs1=”0”THENouty=a1;

ELSEouty=tmp;

ENDIF;

ENDPROCESS;

ENDARCHITECTUREONE;

ENDCASE;

4-4.下图是一个含有上升沿触发的D触发器的时序电路，试写出此电路的VHDL设计文件。

4-4.答案

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYMULTIIS

PORT(CL:INSTD_LOGIC;--输入选择信号

CLK0:INSTD_LOGIC;--输入信号

OUT1:OUTSTD_LOGIC);--输出端

ENDENTITY;

ARCHITECTUREONEOFMULTIIS

SIGNALQ:STD_LOGIC;

BEGIN

PR01:PROCESS(CLK0)

BEGIN

IFCLK‘EVENTANDCLK=’1’

THENQ=NOT(CLORQ);ELSE

ENDIF;

ENDPROCESS;

PR02:PROCESS(CLK0)

BEGIN

OUT1=Q;

ENDPROCESS;

ENDARCHITECTUREONE;

ENDPROCESS;

4-5.给出1位全减器的VHDL描述。要求：

(1)首先设计1位半减器，然后用例化语句将它们连接起来，图3-32中h_suber是半减器，diff是输出差，s_out是借位输出，sub_in是借位输入。

(2)以1位全减器为基本硬件，构成串行借位的8位减法器，要求用例化语句来完成此项设计(减法运算是x–y-sun_in=diffr)

4-5.答案

底层文件1：or2a.VHD实现或门操作

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYor2aIS

PORT(a,b:INSTD_LOGIC;

c:OUTSTD_LOGIC);

ENDENTITYor2a;

ARCHITECTUREoneOFor2aIS

BEGIN

c=aORb;

ENDARCHITECTUREone;

底层文件2：h_subber.VHD实现一位半减器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYh_subberIS

PORT(x,y:INSTD_LOGIC;

diff,s_out::OUTSTD_LOGIC);

ENDENTITYh_subber;

ARCHITECTUREONEOFh_subberIS

SIGNALxyz:STD_LOGIC_VECTOR(1DOWNTO0);

BEGIN

xyz=xy;

PROCESS(xyz)

BEGIN

CASExyzIS

WHEN00=diff=0;s_out=0;

WHEN01=diff=1;s_out=1;

WHEN10=diff=1;s_out=0;

WHEN11=diff=0;s_out=0;

WHENOTHERS=NULL;

ENDCASE;

ENDPROCESS;

ENDARCHITECTUREONE;

顶层文件：f_subber.VHD实现一位全减器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYf_subberIS

PORT(x,y,sub_in:INSTD_LOGIC;

diffr,sub_out:OUTSTD_LOGIC);

ENDENTITYf_subber;

ARCHITECTUREONEOFf_subberIS

COMPONENTh_subber

PORT(x,y:INSTD_LOGIC;

diff,S_out:OUTSTD_LOGIC);

ENDCOMPONENT;

COMPONENTor2a

PORT(a,b:INSTD_LOGIC;

c:OUTSTD_LOGIC);

ENDCOMPONENT;

SIGNALd,e,f:STD_LOGIC;

BEGIN

u1:h_subberPORTMAP(x=x,y=y,diff=d,s_out=e);

u2:h_subberP