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JEDEC
STANDARD
Stress-Test-Driven Qualification of Integrated Circuits
IC集成电路压力测试考核
JESD47I
(Revision of JESD47H.01, April 2011)
JULY 2012
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and approvedby the JEDEC legal counsel.
JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtaining with minimumdelay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoptionmay involve patents or articles, materials, or processes. By such action JEDEC does not assumeany liability to any patent owner, nor does it assume any obligation whatever to parties adoptingthe JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach toproduct specification and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard orpublication may be further processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated inthe standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC at the address below, or refer to underStandards and Documents for alternative contact information.
Published by
?JEDEC Solid State Technology Association 20123103 North 10th Street Suite
240 South
Arlington, VA 22201-2107
This document may be downloaded fre
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