DFT_Compiler使用说明.pdfVIP

DFT_Compiler 使用说明 摘要：本文档介绍了DFT_Compiler 的基本使用，分基本流程框图和基本操作内 容两部分，二者是相互对应的，流程框图是对整个过程的总体说明，操作内容是 是对过程的具体实现以及对为什么要进行对应过程的基本解释。 一、基本流程框图 1 二、基本操作内容 I. Preparing to Run DFT Compiler Before running DFT Compiler, you need to set up your interface, prepare your design environment, and read in your design. This section covers the following topics: • Invoking the Synthesis Tool • Setting Up Your Design Environment • Reading In Your Design • Setting the Scan Style • Configuring the Test Cycle Timing • Defining the DFT Signals 1. Invoking the Synthesis Tool You can use DFT Compiler from within any of the following synthesis tools: * Design Compiler * Design Vision * DC Explorer 2. Setting Up Your Design Environment To set up your design environment, you need to define the paths for the logic libraries and designs you are using, and define any special reporting parameters. # configure logic libraries set search_path /lib_path ##注意对库路径的正确设置 set target_library {library.db} set link_library {* library.db} ##注意*号不能丢，且其后有空格 3. Reading In Your Design To read in your design, specify the appropriate file read commands depending on the file format: read_ddc, read_verilog, read_vhdl. The following example reads in a list of Verilog files: read_verilog {/top_path/top.v /block_path/block.v } ##注意对设计路径的正确设置 Use the current_design and link commands to link the top level of the current design: current_design top link If DFT Compiler is unable to resolve any references, you must provide the missing designs before proceeding. After linking, use the read_sdc command (or the source command) to apply the design constraints: read_sdc top_constraints.sdc Note: If you read in the top-level de