高性能低成本FPGA相关器.pdf

White Paper High Performance, Low Cost FPGA Correlator for Wideband CDMA and Other Wireless Applications Abstract Code division multiple access (CDMA) and the newer wideband code division multiple access (W-CDMA) are wireless communication standards. In both standards, different users are using the same frequency spectrum and different code sequences, to distinguish one user from the other. Match filters are correlator structures used for the purpose of identifying the different code sequences. You can use similar correlator structures for random access channel (RACH) detectors. Match filters or RACH detectors typically require very high computational power. Depending on parameters, the match filter can require execution of tens of billions or hundreds of billions of operations per second. This high computational power requirement is clearly beyond the capability of current digital signal processors. FPGAs can achieve this level of computational power and still maintain the high level of flexibility required to support different variants of these applications. FPGA architectures based on distributed memory (DM) are used in some of these applications to create a high-speed parallel processing architecture. DM architectures are based on Logic Cell RAM elements that can store 16 bits each and can be used as a 16 bit shift register. This paper describes another FPGA architecture based on Parallel samples, Parallel coefficients, and Time division multiplexing (PPT), array calculations using memory blocks that can achieve even higher levels of cost efficiency for these applications. May 2003, ver. 1.0 1 WP-FPGACDMA-1.0 High Performance, Low Cost FPGA Correlator for Wideband CDMA and Other Wireless Applications