基于MIPS流水线处理器设计.docx

PAGE \* MERGEFORMATIV 摘 要 CPU是计算机系统的核心部件，在各类信息终端中得到了广泛的应用。处理器的设计及制造技术也是计算机技术的核心之一。而MIPS是世界上很流行的一种RISC处理器。MIPS的意思是“无内部互锁流水级的微处理器”（Microprocessor without interlocked piped stages），其机制是尽量利用软件办法避免流水线中的数据相关问题。 本文围绕着指令执行过程中需经历的五个阶段，详细描述了处理器中各阶段的逻辑设计及其相关功能模块的设计。这五个阶段包括：取指令阶段IF，指令译码阶段ID，指令执行阶段EXE，存储器读写阶段MEM，寄存器写回阶段WB。相关模块包括：程序存储器imem，控制单元controller，寄存器堆regfile，算术逻辑单元alu，数据存储器dmem。在完成了CPU的整体逻辑设计后，通过Modelsim仿真软件在所设计的CPU上运行了测试程序，测试输出波形表明了处理器逻辑设计的正确性。 关键词：MIPS??处理器；流水线 Abstract The Central Processing Unit (CPU) is the key part of a computer, which has been widely used in various information terminals.Also, the design and manufacturing technology of the processor is one of the cores of the computer technology. And, as a RISC processor, MIPS is very popular in the world. MIPS means “microprocessor without interlocked piped stages”, the mechanism of it is to avoid the data-related problems in the pipeline as much as possible by software. Around the five stages of the instruction execution, the article describes the logic designs of the processor and it’s related functional modules in detail. The five stages include: the instruction fetch stage IF, the instruction decode stage ID, the instruction execution stage EXE, the memory read/write stage MEM, and the register write back stage WB. The related modules include: the instruction memory imem, the control unit controller, the register file regfile, the arithmetic logic unit alu, and the data memory dmem. Upon the completion of the whole logic designs, running the test programs by the Modelsim, the correctness of the logic designs is proved by the output waveform. Keywords: MIPS, CPU, Pipeline 目 录 TOC \o 1-3 \h \z \u   HYPERLINK \l _Toc391197948 摘 要  PAGEREF _Toc391197948 \h I  HYPERLINK \l _Toc391197949 Abstract  PAGEREF _Toc391197949 \h II  HYPERLINK \l _Toc391197950 目 录  PAGEREF _Toc391197950 \h III  HYPERLINK \l _Toc391197951 第1章 MIPS体系结构概述  PAGEREF _Toc391197951 \h 1  HYPERLINK \l _Toc391