ASIC设计第六章：逻辑仿真与时序分析.ppt

* 4.1: 概述 ASIC仿真软件从高到低有以下几类模拟： Behavioral simulation Functional simulation Static timing analysis Gate-level simulation Switch-level simulation Transistor-level or circuit-level simulation *While it is just possible to perform a behavioral-level simulation of a complete system, it is impossible to perform a circuit-level simulation of more than a few hundred transistors. 第四章：逻辑模拟与时序分析 behavioral simulation :models large pieces of a system as black boxes with inputs and outputs. Functional simulation: ignores component’s timing and includes it’s unit-delay simulation , which sets delays to a fixed value (for example, 1 ns). Once a behavioral or functional simulation predicts that a system works correctly, the next step is to check the timing performance. timing simulation: At this point a system is partitioned into ASICs, timing simulation is performed for each ASIC separately. static timing analysis : does not require the creation of a set of test (or stimulus) vectors to compute the delay times for each path. gate-level simulation :be used to check the timing performance of an ASIC. In a gate-level simulator a logic gate or logic cell (NAND, NOR, and so on) is treated as a black box modeled by a function whose variables are the input signals. The function may also model the delay through the logic cell. Setting all the delays to unit value is the equivalent of functional simulation. switch-level simulation : models transistors as switches—on or off. and provides more accurate timing predictions than gate-level simulation. transistor-level simulation : requires models of transistors, describing their nonlinear voltage and current characteristics. The most accurate, but also the most complex and time-consuming. mixed-mode simulator : permits different parts of an ASIC simulation to use different simulation modes. mixed-level simulators: a mixed analog/digital simulator 注意：不要混要以上