EDA课程设计-vhdl语言-12.24小时时钟-乐曲播放电路-函数信号发生器.pdf

附录 一、12/24小时数字时钟VHDL设计 ， 1 系统顶层逻辑图： 时序仿真波形 管脚定义以及锁定 2，分频模块。 ①各个分频模块的模块图： ②，分别对应的仿真波形： ③50mhz分频至1k模块代码： end process; library ieee; process(co) use ieee.std_logic_unsigned.all; begin use ieee.std_logic_1164.all; if coevent and co=1 then entity wh4574_divto1k is count2=not count2; port(clk50m:in std_logic; end if; clk1k:out std_logic); end process; end wh4574_divto1k; clk1k=count2; architecture behav of wh4574_divto1k is end behav; signal count1:std_logic_vector(14 downto 0); 50mhz分频至2k模块代码： signal count2:std_logic; library ieee; signal co:std_logic; use ieee.std_logic_unsigned.all; begin use ieee.std_logic_1164.all; process(clk50m) entity wh4574_divto2k is begin port(clk50m:in std_logic; if clk50mevent and clk50m=1 then clk2k:out std_logic); if count1=110000110100111 then end wh4574_divto2k; count1=000000000000000; architecture behav of wh4574_divto2k is co=1; signal count1:std_logic_vector(13 downto else 0); count1=count1+1; signal count2:std_logic; co=0; signal co:std_logic; end if; begin end if;