三输入与非门版图.docx

三输入与非门的版图1、版图2、Spice网表文件* Circuit Extracted by Tanner Researchs L-Edit Version 13.00 / Extract Version 13.00 ;* TDB File: G:\bantu\NAND3.1.tdb* Cell: Cell0Version 1.36* Extract Definition File: C:\Users\tbmei\Documents\Tanner EDA\Tanner Tools v13.0\L-Edit and LVS\SPR\Lights\Layout\lights.ext* Extract Date and Time: 06/09/2014 - 18:17.include G:\bantu\ml5_20.md* Warning: Layers with Unassigned FRINGE Capacitance.* Pad Comment* Poly1-Poly2 Capacitor ID* NODE NAME ALIASES* 1 = vdd (0 , 60)* 2 = Gnd (0 , 0)* 3 = OUT (14 , 20)* 4 = C (40 , 31)* 5 = B (27 , 31)* 6 = A (2 , 38)M1 OUT C1 vdd vdd PMOS L=3u W=20u AD=96p PD=52u AS=100p PS=30u $ (37 46 40 66)M2 vdd B OUT vdd PMOS L=3u W=20u AD=100p PD=30u AS=110p PS=31u $ (24 46 27 66)M3 OUT A vdd vdd PMOS L=3u W=20u AD=110p PD=31u AS=108p PS=54u $ (10 46 13 66)M4 OUT C1 9 8 NMOS L=3u W=20u AD=120p PD=56u AS=100p PS=30u $ (37 0 40 20)M5 9 B 7 8 NMOS L=3u W=20u AD=100p PD=30u AS=110p PS=31u $ (24 0 27 20)M6 7 A Gnd 8 NMOS L=3u W=20u AD=110p PD=31u AS=172p PS=60u $ (10 0 13 20).include G:\bantu\ml5_20.md.tran 600n 600n start=0VDDD vdd Gnd 3VAin A Gnd pwl (0ns 0V 100ns 0V 105ns 3V 200ns 3V 205ns 0V 300ns 0V 305ns 3V 400ns 3V 405ns 0V 500ns 0V 505ns 3V 600ns 3V)VBin B Gnd pwl (0ns 0V 100ns 0V 105ns 0V 200ns 0V 205ns 3V 300ns 3V 305ns 3V 400ns 3V 405ns 0V 500ns 0V 505ns 3V 600ns 3V)VCin C1 Gnd pwl (0ns 0V 100ns 0V 105ns 0V 200ns 0V 205ns 0V 300ns 0V 305ns 0V 400ns 0V 405ns 3V 500ns 3V 505ns 3V 600ns 3V).print tran v(A,Gnd).print tran v(B,Gnd).print tran v(C1,Gnd).print tran v(OUT,Gnd)* Pins of element D2 are shorted:* D2 vdd vdd D_lateral $ (3 58 7 66)* Total Nodes: 9* Total Elements: 8* Total Number of Shorted Elements not written to the SPICE file: 0* Output Generation Elapsed Time: 0.000 sec* Total Extract Elapsed Time: 0.687 sec.END3、仿真波形图4、波形分析输入信号A、B、C1中至少一个为低电平时，输出OUT为高电平；只有输入信号A、B、C1同时为高电平时，输出OUT为低电平。