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基于FPGA的自动打铃系统的设计与实现
自动打铃系统设计说明书
学 生 姓 名: 罗 衡
学 号:14092500060
专 业 班 级:电子09-2BF
报告提交日期:2011-11-28
湖 南 理 工 学 院 物 电 学 院
目 录
一、题目及要求简介··············································· 1
设计题目···················································· 1
2.总体要求简介················································ 1
二、设计方案说明················································· 1
三、各部分功能介绍及程序······································· 2
1.系统框图···················································· 2
2.选择的FPGA芯片及配置······································· 2
3.各模块(元件)说明·········································· 2
四、仿真结果····················································· 4
1.计时进位···················································· 4
2.手动校时···················································· 5
3.六点整闹铃·················································· 5
五、说明·························································· 5
1.输入激励信号说明············································ 5
2.输出结果说明················································ 6
六、源程序························································ 6
1.顶层模块···················································· 6
模式控制子模块·············································· 7
计时及调整子模块············································ 8
闹铃及调整子模块············································ 10
显示子模块·················································· 11
七、参考文献····················································· 14
一、设计题目及要求简介
1.设计题目
基于FPGA的自动打铃系统的设计与实现
2.总体要求简介
(1)基本计时和显示功能
① 24小时制显示
② 动态扫描显示
③ 显示格式:88-88-88
(2)能设置当前时间(含时、分)
(3)能实现基本打铃功能,上午06:00起床铃,打铃5秒
设计方案说明
本系统采用自顶向下的模块化设计方法,将数字闹钟按照功能实现分为模式控制模块、计时及调整模块、闹铃及调整模块、显示模块。系统调整部分软件控制流程示意图如图2-1所示。
图2-1
各部分功能介绍及程序
1.系统框图
顶层电路主要由FPGA实现,输出信号接到八位数码管、LED指示灯及扬声器上,系统框图如图3-1所示。
图3-1
选择的FPGA芯片及配置
本系统选择ACEX1K系列的EP1K10TC100-3芯片,由于FPGA器件是基于SRAM结构的,具有易失性,在此采用被动串行配置(PS)方式,由外部的计算机控制配置过程,使用USB-Blaster下载电缆下载程序。
3.各模块(元件)说明
3.1 顶层文件端口说明
module alarmclock(clk,clk_1k,mode,change,turn,sel,decodeout,alert,
LD_alert,LD_hour,LD_min);
input clk,clk_1k,mode,change,turn;
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