外文文献原文基于FPGA逻辑分析仪设计与实现--中英文翻译.doc

本科毕业设计（论文）外文翻译 题 目 学生姓名 班 级 学 号 院 （系） 专 业 指导教师 职 称 2017年 月 日 原文： Clock Buffer Basics [author] :Hamilton, Mark1( markh@rennes.ucc.ie);Marnane, William P.1( HYPERLINK mailto:liam@eleceng.ucc.ie) liam@eleceng.ucc.ie) [press] :clock buffer with FPGA Clocks are the basic building blocks for all electronics today. For every data transition in a synchronous digital system, there is a clock that controls a register. Most systems use Crystals, Frequency Timing Generators (FTGs), or inexpensive ceramic resonators to generate precision clocks for their synchronous systems. Additionally, clock buffers are used to create multiple copies, multiply and divide clock frequencies, and even move clock edges forwards or backward in time. Many clock-buffering solutions have been created over the past few years to address the many challenges required by today’s high-speed logic systems. Some of these challenges include: High operating and output frequencies, propagation delays from input to output, output to output skew between pins, cycle-tocycle and long-term jitter, spread spectrum, output drive strength, I/O voltage standards, and redundancy. Because clocks are the fastest signals in a system and are usually under the heaviest loads, special consideration must be given when creating clocking trees. In this chapter, we outline the basic functions of non-PLL and PLL-based buffers and show how these devices can be used to address the high-speed logic design challenges. In today’s typical synchronous designs, multiple clock signals are often needed to drive a variety of components. To create the required number of copies, a clock tree is constructed. The tree begins with a clock source such as an oscillator or an exte