pll frequency synthesizer.pdf

Chapter 3 PLL FREQUENCY SYNTHESIZER This chapter presents the analysis of PLL-based frequency synthesizers. It includes the continuous-time linear analysis, discrete-time analysis, operation modes, stability, and fast-locking techniques. An integer-N PLL synthesizer design example is given to illustrate the system-level parameter design procedure. PLL frequency synthesizer basics Basic building blocks of charge-pump PLL The block diagram of the PLL frequency synthesizer is shown in Fig. 3-1. It is based on a charge-pump PLL [ l ] and consists of a phase-frequency detector (PFD), a charge-pump (CP), a loop filter (LF), a voltage-controlled oscillator (VCO), a dual-modulus prescaler, and a programmable pulse- swallowing divider. The divide ratio of the dual-modulus prescaler is P or P+l . M and A are programmable integers [2], [3]. Each divider output cycle consists of (P+l).A+P.(M-A) VCO cycles. Thus the nominal frequency divide ratio is: N = M . P + A The synthesizer output frequency is f o u r = N . f i n = ( M . P + A ) . f i t , Chapter 3 f~ charge loop f0,t - PFD - - VCo - pump - filter Figure 3-1. Charge-pump PLL frequency synthesizer Figure 3-2. Tri-state phase-frequency detector (PFD) The phase detector (PD) detects the phase difference between the reference signal and the feedback signal from the VCO and frequency divider. Note that, although the PD of a PLL can be an analog multiplier, an exclusive-or (XOR) gate or a J-K flip-flop, etc, for a frequency synthesizer we always use the charge-pump PLL with a tri-state phase-frequency detector (PFD) that also detects frequency errors [3] . Note that, this tri-state PFD is also referred to as type-4 PD in the literature. The charge-pump PLL has two poles at the origin (type-11) in its open-loop transfer function. It locks faster and its static phase error is zero if mismatches and leakages are negligible. Moreover, its capture range is only limited by its VCO tuning r