xstsynthesis.ppt

XST Synthesis FPGA Design Workshop Objectives After completing this module, you will be able to… Xilinx Design Process Step1: Design Two design entry methods: HDL(Verilog or VHDL) or schematic drawings Step 2: Synthesize to create Netlist Translates V, VHD, SCH files into an industry standard format EDIF file Step 3: Implement design (netlist) Translate, Map, Place Route Step 4: Configure FPGA Download BIT file into FPGA XST Features RAM inferencing Schematic viewer Error navigation Timing-driven synthesis Fanout control Note: Mixed language designs are not supported XST Synthesis in Project Navigator Module/entity selected in Sources window treated as “top” XST-specific processes Synthesize View Synthesis Report Analyze Hierarchy Check Syntax XST-specific properties Synthesis Options HDL Options Xilinx Specific Options Device Support FPGAs Virtex Virtex-E Virtex-II Virtex-II Pro Spartan-II Spartan-IIE CPLDs XC9500 XC9500XL XC9500XV CoolRunner CoolRunner-II XST Flow Main Synthesis Steps Macro Inference Macro inference consists of two main steps: Recognition (HDL synthesis level): XST tries to recognize as many macros as possible Implementation (low level optimization): XST makes technology dependent choices Improve design performance and decrease area Preserve the macro as a macro? Merge the macro with surrounded logic? Choices depends on the macro type and size If XST decides to preserve the macro, you must decide the way the macro is to be implemented Macro Inference FSM Recognition XST is able to recognize state machines independent of the modeling style used For example, you may have several processes (one, two, or three) in your description, depending on how you consider and decompose Notes XST can handle/recognize synchronous state machines Currently, XST requires FSM with initialization signals, which can be asynchronous or synchronous FSM Optimization Optimization is based on: State assignment Flip-flop (FF) type selection St