电子科技大学“数字逻辑设计及应用”数字逻辑X-2.pptVIP

* * Text entry with Verilog HDL Chapter 5 Design simulation and HDL Verilog HDL structure Use text entry to replace schematic entry: Large design and time delay can be easily described ; Modification can be easily done. Verilog HDL structure Hardware module： Name、port 、 structure 、function Module name and IO module majority (a,b,c,f); input a,b,c; output f; … … endmodule Signal :port and wire Two kinds of signal : port : input and output; wire : any connect nets in module; The value of signals: 0 1 z x module majority (a,b,c,f); input a,b,c; output f; wire w1,w2,w3; … … endmodule Signal :port and wire Use built_in gates for design Structure description module majority (a,b,c,f); input a,b,c; output f; wire w1,w2,w3; and u1(w1,a,b); and u2(w2,b,c); and u3(w3,a,c); or u4(f,w1,w2,w3); endmodule Logic operators for bit data: y = a b; y = a | b; y = ~ a; y = a ^ b; Logic operations Dataflow description module majority (a,b,c,f); input a,b,c; output f; wire w1,w2,w3; assign w1=ab; assign w2=bc; assign w3=ac; assign f=w1|w2|w3; endmodule module majority (a,b,c,f); input a,b,c; output f; assign f=(ab)|(bc)|(ac); endmodule Dataflow description 4-bits prime-number detector when input is (1,2,3,5,7,11,13), the output is 1, otherwise the output is 0 . Bus signal and its operations module prime (a,f); input [3:0] a; output f; wire [3:0] w; assign w[0]=~a[3]a[0]; assign w[1]=a[2]~a[1]a[0]; assign w[2]=~a[3]~a[2]a[1]; assign w[3]=~a[2]a[1]a[0]; assign f=w[3]|w[2]|w[1]|w[0]; endmodule Bus signal and its operations Text entry Bus signal set Bus signal set module bus (a,b,y1,y2,y3); input[7:0] a,b; output[7:0] y1,y2,y3; assign y1=a b; assign y2=a | b; assign y3=~a; endmodule Bus signal and its operations Bus signal and its operations