电子科技大学“数字逻辑设计及应用”数字逻辑2-1.pptVIP

MOS device and CMOS Structure Chapter 2 Digital circuit design for logic unit Logic levels 1 High level 0 Low level ideal level : 1 Vcc 0 Gnd Simple logic circuits Output level can not be ideal Too much power consumptions Switch circuit Any node in circuit must get 1/0 from Vcc/Gnd by switches Switch : MOS transistor Switch : MOS transistor Switch is controlled by G through electric field;  PMOS: when G is 0, Switch on; when G is 1, Switch off; NMOS: when G is 1, Switch on; when G is 0, Switch off; Two types of MOS transistor CMOS inverter (INV) CMOS NAND / NOR Output with positive logic Buffer AND Each input control a PMOS and an NMOS; Logic is represented by NMOS connections : AND -- series OR -- parallel PMOS is a duality connection. Summary for CMOS circuits CMOS devices with 3 inputs NAND / NOR NAND: NMOS serial ; NOR: NMOS parallel; AOI / OAI Design with transistors Open gate and wired logic Design with transistors Open gate design Open gate and wired logic The outputs can be connected to get AND logic . CMOS transmission gate (TG) Three state output: 0 / 1 / Z c=1 pass c=0 cutoff Three state inverter * * *