C H A P T E R 13Output Stages and Power Amplifiers.ppt

* sedr42021_1420.jpg * sedr42021_1421.jpg * sedr42021_1422.jpg * * sedr42021_1423.jpg * * sedr42021_1424.jpg * * sedr42021_1425.jpg * * sedr42021_1427.jpg * * sedr42021_1428.jpg * * sedr42021_1429.jpg * * sedr42021_1430.jpg * sedr42021_1431.jpg * sedr42021_1433.jpg * sedr42021_1434.jpg * sedr42021_1435.jpg * sedr42021_1436.jpg * sedr42021_1437.jpg * sedr42021_1438.jpg * Figure 13.29 Safe operating area (SOA) of a BJT. i0 V0 Melting wire (P Dmax) Emitter crowding (hot spot) VBE * Figure 13.30 A class AB output stage with an input buffer. In addition to providing a high input resistance, the buffer transistors Q1 and Q2 bias the output transistors Q3 and Q4. Bias VBB 負回授 . *Ri * Figure 13.31 The Darlington configuration. Microelectronic Circuits, International Sixth Edition Figure 13.32 The compound-pnp configuration. * Figure 13.33 A class AB output stage utilizing a Darlington npn and a compound pnp. Biasing is obtained using a VBE multiplier. Darlington compound * Figure 13.34 A class AB output stage with short-circuit protection. The protection circuit shown operates in the event of an output short circuit while vO is positive. 平時 Q5 off iL ↑↑(及 ie1很大) →Vbe5 ↑(Q5ON) →ib1↓→ie1 ↓ ib1 ics ie1 * Figure 13.35 Thermal-shutdown circuit. Power Amp. Vcs Sink IQ (並聯) 導熱 平時 Q2 off temp↑→VZ1↑→Ie1↑→Vb2↑ →Q2 ON * Figure 13.36 The simplified internal circuit of the LM380 IC power amplifier. (Courtesy National Semiconductor Corporation.) (14.45) V0=VS/2 Q3.Q4:diff. amp. Q1.Q2:Vi buffer Q5.Q6:active load I3 負回授 I4為負F.B. V0↑→i4↑ →ic4↑ →ic12↑(I3固定) →ib7↓ →V0↓ 主 O/P i/P I3 * Figure 13.37 Small-signal analysis of the circuit in Fig. 14.30. The circled numbers indicate the order of the analysis steps. 6 + 9 = 10 Vi/R3 +V0/r2 +Vi/R3=0 10 14 Av=-50 Microelectronic Circuits, International Sixth Edition Figure 13.38 Power dissipation (PD) versus output power (PL) for the LM380 with RL = 8V. (Courtesy National Semicond