elec5970-0036970-003-auburnuniversity（5页）.doc

ELEC5970-003/6970-003 Homework 2, assigned 11/02/04, due 11/30/04 Problem 1: ISA for Low Power Contributed by Hillary Grimes, grimehh@ When designing an instruction set architecture, describe how reducing instruction word length could improve energy efficiency. ?How could a reduced instruction word length have a negligible impact on energy efficiency? Reference: T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: ?Kluwer Academic Publishers, 2002. Problem 2: Spectral BIST Contributed by Ayoush Dixit, dixitam@ Spectral BIST algorithms came about when it was realized that random testing resulted in poor fault coverage in circuits with random-pattern resistant faults. How well can the spectral BIST algorithm discussed in the literature (see references [1] and [2]) handle the non-randomness in the test vectors without losing the fault coverage considerably?  References: [1] A. Giani, S. Sheng, M. S. Hsiao, and V. D. Agrawal, “Efficient Spectral Techniques for Sequential ATPG,” Proc. Design, Automation and Test in Europe (DATE) Conf., March 2001, pp. 204-208.[2] ? A. Giani, S. Sheng, M. S. Hsiao, and V. D. Agrawal, “Novel Spectral methods for Built-In Self-Test in a System-on-a-Chip Environment,” Proc. 19th IEEE VLSI Test Symp., April 2001, pp. 163-168 Problem 3: Leakage Power Contributed by Yuanlin Lu, luyuanl@ Read the following paper, specifically paying attention to the transistor stacking effect. Then decide which among the four input vectors {00, 01,10, 11} will lead to the maximum and minimum leakage currents in a two-input CMOS NOR gate in the standby mode. Without any hand calculation, estimate the values by intuition. You can also verify your result by SPICE simulation. Assume that each nMOS and pMOS transistor has already been properly sized to have the same subthreshold current. Reference: Richard X. Gu, et al., “Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits,” IEEE