Lectue 4 The VHDL N-bit adder.ppt

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Lectue 4 The VHDL N-bit adder.ppt

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Lectue 4 The VHDL N-bit adder

CWRU EECS 317 LECTURE 4: The VHDL N-bit Adder Review: N-Bit Ripple-Carry Adder Hierarchical design: 2-bit adder LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY adder_bits_2 IS PORT (Cin: IN std_logic; a0, b0, a1, b1: IN std_logic; S0, S1: OUT std_logic; Cout: OUT std_logic ); END; Hierarchical design: Component Instance ARCHITECTURE ripple_2_arch OF adder_bits_2 IS COMPONENT full_adder PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic); END COMPONENT; SIGNAL t1: std_logic; BEGINFA1: full_adder PORT MAP (Cin, a0, b0, S0, t1); FA2: full_adder PORT MAP (t1, a1, b1, s1, Cout); END; Positional versus Named Association FA1: full_adder PORT MAP (Cin, a0, b0, S0, t1); Component by Named Association ARCHITECTURE ripple_2_arch OF adder_bits_2 IS COMPONENT full_adder PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic); END COMPONENT; SIGNAL t1: std_logic; -- Temporary carry signal BEGIN -- Named associationFA1: full_adder PORT MAP (Cin=x, a0=y, b0=z, S0=Sum, t1=Carry);-- Positional associationFA2: full_adder PORT MAP (t1, a1, b1, s1, Cout); END; Using vectors: std_logic_vector ENTITY adder_bits_2 IS PORT (Cin: IN std_logic; a0, b0, a1, b1: IN std_logic; S0, S1: OUT std_logic; Cout: OUT std_logic ); END; 2-bit Ripple adder using std_logic_vector ARCHITECTURE ripple_2_arch OF adder_bits_2 IS COMPONENT full_adder PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic); END COMPONENT; SIGNAL t1: std_logic; -- Temporary carry signal BEGIN FA1: full_adder PORT MAP (Cin, a(0), b(0), S(0), t1);FA2: full_adder PORT MAP (t1, a(1), b(1), s(1), Cout); END; 4-bit Ripple adder using std_logic_vector ARCHITECTURE ripple_4_arch OF adder_bits_4 IS COMPONENT full_adder PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic); END COMPONENT; SIGNAL t: std_logic_vector(3 downto 1); BEGIN FA1: full_adder PORT MAP (Cin, a(0), b(0), S(0), t(1));FA2: full_adder PORT MAP (t(1), a(1), b(1), S(