《TI High-Speed Board Design》.pdf

High Speed Design Seminar BuS Solutions High-Speed Board Design Bill Simms Serial Gigabit Solutions High Speed Design Seminar High Speed Board Design BuS Solutions Layout and Routing Filtering Component Placement 07/22/1999 Serial Gigabit Solutions High Speed Design Seminar Board Stackups BuS Solutions Layer # 1 2 3 4 5 6 7 8 9 10 Comments 4 Layer S1 G P S2 Difficult to maintain high signal impedance and low power impedance 6 Layer S1 G S2 S3 P S4 Lower Speed Design, poor power, high signal impedance 6 Layer S1 S2 G P S3 S4 Default critical signals on S2 only 6 Layer S1 G S2 P G S3 Default lower-speed signals to S2 only Preferred 8 Layer S1 S2 G S3 S4 P S5 S6 Default high-speed signals to S2-S3. Has poor power impedance 8 Layer S1 G S2 G P S3 G S4 Best for EMC Preferred 10 Layer S1 G S2 S3 G P S4 S5 G S6 Best for EMC. S4 susceptible to power noise 07/22/1999 Serial Gigabit Solutions